The present invention relates to an EPROM memory array with crosspoint configuration and to a method for its manufacture.
As is known, EPROM arrays with crosspoint configuration have source and drain lines which define the bit lines, extend mutually parallel and alternated and are perpendicular to the word lines defined by gate lines.
It is also known that in EPROM cells it is necessary to make two requirements coexist: on one hand, to have a high read current to optimize the speed of the cell, on the other to have a structure which allows sufficient multiplication and therefore ensures a good writing efficiency of the cell.
These requirements are mutually opposite, since the first condition is favored by low channel doping levels, whereas the second requires high doping levels in the channel proximate to the drain junction. A doping level which provides the best compromise between these two requirements is therefore usually adopted.
A better solution consists in doping the channel more heavily only on the drain side. This higher doping does not reflect in a decrease of the read current, since the affected region, being proximate to the drain junction, depletes during reading. Furthermore, in the case of cells with asymmetrical doping, it is also possible to invert the source and the drain during reading and writing, using, as the drain, the more heavy doped side during writing and the less doped side during reading, so as to minimize unwanted writing of unselected cells (so-called "soft writing").
Cells with asymmetrical dopings of this kind have been manufactured using a mask which is aligned with the center line of the gate, covering the side toward the source and leaving open the channel toward the drain. However, as the size decreases it becomes extremely critical to align a mask on a gate the width whereof can be less then 0.8.mu..
Conventional EPROM cells furthermore have the disadvantage of not allowing size reduction due to the criticalities caused by the small size of the contacts, by the difficulties in shaping complex cell geometries with overlapping gates and by the high density of the contacts.
In order to solve this problem, a structure has already been proposed (see the article "High Density Contactless, Self Aligned EPROM Cell Array Technology", J. Esquivel et al., IEEE, 1986, pages 592-995) with bit lines buried under a thick oxide grown with a local oxidation method, so that the memory cell is symmetrical with respect to the source and drain diffusions. This structure advantageously solves the problem of reducing the array size, allowing an area saving of up to 33% with respect to the preceding conventional solutions, but does not allow the asymmetrical doping of the drain lines with respect to the source ones and therefore does not provide optimum results as regards the electric characteristics of the memory array.